Integrated Switching Architecture and Its Traffic Handling Capacity in Data Communication Networks

Noriharu MIYAHO; Akira MIURA

Integrated Switching Architecture and Its Traffic Handling Capacity in Data Communication Networks

Noriharu MIYAHO, Akira MIURA

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A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

Publication: IEICE TRANSACTIONS on Communications Vol.E79-B No.12 pp.1887-1899

Publication Date: 1996/12/25

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Type of Manuscript: PAPER

Category: Communication Systems and Transmission Equipment

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Noriharu MIYAHO, Akira MIURA, "Integrated Switching Architecture and Its Traffic Handling Capacity in Data Communication Networks" in IEICE TRANSACTIONS on Communications, vol. E79-B, no. 12, pp. 1887-1899, December 1996, doi: .
Abstract: A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/e79-b_12_1887/_p

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@ARTICLE{e79-b_12_1887,
author={Noriharu MIYAHO, Akira MIURA, },
journal={IEICE TRANSACTIONS on Communications},
title={Integrated Switching Architecture and Its Traffic Handling Capacity in Data Communication Networks},
year={1996},
volume={E79-B},
number={12},
pages={1887-1899},
abstract={A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Integrated Switching Architecture and Its Traffic Handling Capacity in Data Communication Networks
T2 - IEICE TRANSACTIONS on Communications
SP - 1887
EP - 1899
AU - Noriharu MIYAHO
AU - Akira MIURA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E79-B
IS - 12
JA - IEICE TRANSACTIONS on Communications
Y1 - December 1996
AB - A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.
ER -