A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor

Hideharu AMANO; Akiya JOURAKU; Kenichiro ANJO

A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor

Hideharu AMANO, Akiya JOURAKU, Kenichiro ANJO

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A framework of dynamically adaptive hardware mechanism on multicontext reconfigurable devices is proposed, and as an example, an adaptive switching fabric is implemented on NEC's novel reconfigurable device DRP (Dynamically Reconfigurable Processor). In this switch, contexts for the full crossbar and alternative hadware modules, which provide larger bandwidth but can treat only a limited pattern of packet inputs, are prepared. Using the quick context switching functionality, a context for the full crossbar is replaced by alternative contexts according to the packet inputs pattern. If the context corresponding to requested alternative hadware modules is not inside the chip, it is loaded from outside chip to currently unused context memory, then replaced with the full size crossbar. If the traffic includes a lot of packets for specific destinations, a set of contexts frequently used in the traffic is gathered inside the chip like a working set stored in a cache. 4 4 mesh network connected with the proposed adaptive switches is simulated, and it appears that the latency between nodes is improved three times when the traffic between neighboring four nodes is dominant.

Publication: IEICE TRANSACTIONS on Communications Vol.E86-B No.12 pp.3385-3391

Publication Date: 2003/12/01

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on Software Defined Radio Technology and Its Applications)

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Hideharu AMANO, Akiya JOURAKU, Kenichiro ANJO, "A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor" in IEICE TRANSACTIONS on Communications, vol. E86-B, no. 12, pp. 3385-3391, December 2003, doi: .
Abstract: A framework of dynamically adaptive hardware mechanism on multicontext reconfigurable devices is proposed, and as an example, an adaptive switching fabric is implemented on NEC's novel reconfigurable device DRP (Dynamically Reconfigurable Processor). In this switch, contexts for the full crossbar and alternative hadware modules, which provide larger bandwidth but can treat only a limited pattern of packet inputs, are prepared. Using the quick context switching functionality, a context for the full crossbar is replaced by alternative contexts according to the packet inputs pattern. If the context corresponding to requested alternative hadware modules is not inside the chip, it is loaded from outside chip to currently unused context memory, then replaced with the full size crossbar. If the traffic includes a lot of packets for specific destinations, a set of contexts frequently used in the traffic is gathered inside the chip like a working set stored in a cache. 4 4 mesh network connected with the proposed adaptive switches is simulated, and it appears that the latency between nodes is improved three times when the traffic between neighboring four nodes is dominant.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/e86-b_12_3385/_p

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@ARTICLE{e86-b_12_3385,
author={Hideharu AMANO, Akiya JOURAKU, Kenichiro ANJO, },
journal={IEICE TRANSACTIONS on Communications},
title={A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor},
year={2003},
volume={E86-B},
number={12},
pages={3385-3391},
abstract={A framework of dynamically adaptive hardware mechanism on multicontext reconfigurable devices is proposed, and as an example, an adaptive switching fabric is implemented on NEC's novel reconfigurable device DRP (Dynamically Reconfigurable Processor). In this switch, contexts for the full crossbar and alternative hadware modules, which provide larger bandwidth but can treat only a limited pattern of packet inputs, are prepared. Using the quick context switching functionality, a context for the full crossbar is replaced by alternative contexts according to the packet inputs pattern. If the context corresponding to requested alternative hadware modules is not inside the chip, it is loaded from outside chip to currently unused context memory, then replaced with the full size crossbar. If the traffic includes a lot of packets for specific destinations, a set of contexts frequently used in the traffic is gathered inside the chip like a working set stored in a cache. 4 4 mesh network connected with the proposed adaptive switches is simulated, and it appears that the latency between nodes is improved three times when the traffic between neighboring four nodes is dominant.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor
T2 - IEICE TRANSACTIONS on Communications
SP - 3385
EP - 3391
AU - Hideharu AMANO
AU - Akiya JOURAKU
AU - Kenichiro ANJO
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E86-B
IS - 12
JA - IEICE TRANSACTIONS on Communications
Y1 - December 2003
AB - A framework of dynamically adaptive hardware mechanism on multicontext reconfigurable devices is proposed, and as an example, an adaptive switching fabric is implemented on NEC's novel reconfigurable device DRP (Dynamically Reconfigurable Processor). In this switch, contexts for the full crossbar and alternative hadware modules, which provide larger bandwidth but can treat only a limited pattern of packet inputs, are prepared. Using the quick context switching functionality, a context for the full crossbar is replaced by alternative contexts according to the packet inputs pattern. If the context corresponding to requested alternative hadware modules is not inside the chip, it is loaded from outside chip to currently unused context memory, then replaced with the full size crossbar. If the traffic includes a lot of packets for specific destinations, a set of contexts frequently used in the traffic is gathered inside the chip like a working set stored in a cache. 4 4 mesh network connected with the proposed adaptive switches is simulated, and it appears that the latency between nodes is improved three times when the traffic between neighboring four nodes is dominant.
ER -