A new high-throughput turbo decoding scheme adopting double flow, sliding window and shuffled decoding is proposed. Analytical and numerical results show that the proposed scheme requires low number of clock cycles and small memory size to achieve a BER performance equivalent to those of existing schemes.
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Jaesung CHOI, Joonyoung SHIN, Jeong Woo LEE, "High Throughput Turbo Decoding Scheme" in IEICE TRANSACTIONS on Communications,
vol. E95-B, no. 6, pp. 2109-2112, June 2012, doi: 10.1587/transcom.E95.B.2109.
Abstract: A new high-throughput turbo decoding scheme adopting double flow, sliding window and shuffled decoding is proposed. Analytical and numerical results show that the proposed scheme requires low number of clock cycles and small memory size to achieve a BER performance equivalent to those of existing schemes.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/transcom.E95.B.2109/_p
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@ARTICLE{e95-b_6_2109,
author={Jaesung CHOI, Joonyoung SHIN, Jeong Woo LEE, },
journal={IEICE TRANSACTIONS on Communications},
title={High Throughput Turbo Decoding Scheme},
year={2012},
volume={E95-B},
number={6},
pages={2109-2112},
abstract={A new high-throughput turbo decoding scheme adopting double flow, sliding window and shuffled decoding is proposed. Analytical and numerical results show that the proposed scheme requires low number of clock cycles and small memory size to achieve a BER performance equivalent to those of existing schemes.},
keywords={},
doi={10.1587/transcom.E95.B.2109},
ISSN={1745-1345},
month={June},}
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TY - JOUR
TI - High Throughput Turbo Decoding Scheme
T2 - IEICE TRANSACTIONS on Communications
SP - 2109
EP - 2112
AU - Jaesung CHOI
AU - Joonyoung SHIN
AU - Jeong Woo LEE
PY - 2012
DO - 10.1587/transcom.E95.B.2109
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E95-B
IS - 6
JA - IEICE TRANSACTIONS on Communications
Y1 - June 2012
AB - A new high-throughput turbo decoding scheme adopting double flow, sliding window and shuffled decoding is proposed. Analytical and numerical results show that the proposed scheme requires low number of clock cycles and small memory size to achieve a BER performance equivalent to those of existing schemes.
ER -