A Memory-Efficient Bit-Split Pattern Matching Architecture Using Shared Match Vectors for Deep Packet Inspection

HyunJin KIM

doi:10.1587/transcom.E95.B.3594

A Memory-Efficient Bit-Split Pattern Matching Architecture Using Shared Match Vectors for Deep Packet Inspection

HyunJin KIM

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This paper proposes a bit-split string matcher architecture for a memory-efficient hardware-based parallel pattern matching engine. In the proposed bit-split string matcher, multiple finite-state machine (FSM) tiles share match vectors to reduce the required number of stored match vectors. By decreasing the memory size for storing match vectors, the total memory requirement can be minimized.

Publication: IEICE TRANSACTIONS on Communications Vol.E95-B No.11 pp.3594-3596

Publication Date: 2012/11/01

Publicized

Online ISSN: 1745-1345

DOI: 10.1587/transcom.E95.B.3594

Type of Manuscript: LETTER

Category: Network Management/Operation

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HyunJin KIM, "A Memory-Efficient Bit-Split Pattern Matching Architecture Using Shared Match Vectors for Deep Packet Inspection" in IEICE TRANSACTIONS on Communications, vol. E95-B, no. 11, pp. 3594-3596, November 2012, doi: 10.1587/transcom.E95.B.3594.
Abstract: This paper proposes a bit-split string matcher architecture for a memory-efficient hardware-based parallel pattern matching engine. In the proposed bit-split string matcher, multiple finite-state machine (FSM) tiles share match vectors to reduce the required number of stored match vectors. By decreasing the memory size for storing match vectors, the total memory requirement can be minimized.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/transcom.E95.B.3594/_p

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@ARTICLE{e95-b_11_3594,
author={HyunJin KIM, },
journal={IEICE TRANSACTIONS on Communications},
title={A Memory-Efficient Bit-Split Pattern Matching Architecture Using Shared Match Vectors for Deep Packet Inspection},
year={2012},
volume={E95-B},
number={11},
pages={3594-3596},
abstract={This paper proposes a bit-split string matcher architecture for a memory-efficient hardware-based parallel pattern matching engine. In the proposed bit-split string matcher, multiple finite-state machine (FSM) tiles share match vectors to reduce the required number of stored match vectors. By decreasing the memory size for storing match vectors, the total memory requirement can be minimized.},
keywords={},
doi={10.1587/transcom.E95.B.3594},
ISSN={1745-1345},
month={November},}

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TY - JOUR
TI - A Memory-Efficient Bit-Split Pattern Matching Architecture Using Shared Match Vectors for Deep Packet Inspection
T2 - IEICE TRANSACTIONS on Communications
SP - 3594
EP - 3596
AU - HyunJin KIM
PY - 2012
DO - 10.1587/transcom.E95.B.3594
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E95-B
IS - 11
JA - IEICE TRANSACTIONS on Communications
Y1 - November 2012
AB - This paper proposes a bit-split string matcher architecture for a memory-efficient hardware-based parallel pattern matching engine. In the proposed bit-split string matcher, multiple finite-state machine (FSM) tiles share match vectors to reduce the required number of stored match vectors. By decreasing the memory size for storing match vectors, the total memory requirement can be minimized.
ER -