Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping

Canh Quang TRAN; Hiroshi KAWAGUCHI; Takayasu SAKURAI

doi:10.1093/ietele/e89-c.3.280

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_TH/V_DD and Micro-V_DD-Hopping

Canh Quang TRAN, Hiroshi KAWAGUCHI, Takayasu SAKURAI

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A low-power FPGA design approach is proposed based on a fine-grain V_DD control scheme called micro-V_DD-hopping. Four configurable logic blocks (CLBs) are grouped into one block where V_DD is shared. In the micro-V_DD-hopping scheme, V_DD in each block is changed between V_DDH (high V_DD) and V_DDL (low V_DD) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for low-swing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakage-path problem. A test chip was fabricated using a 0.35-µm CMOS technology, together with the conventional fixed-V_DD FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.280-286

Publication Date: 2006/03/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.3.280

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)

Category: Low Power Techniques

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Canh Quang TRAN, Hiroshi KAWAGUCHI, Takayasu SAKURAI, "Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 3, pp. 280-286, March 2006, doi: 10.1093/ietele/e89-c.3.280.
Abstract: A low-power FPGA design approach is proposed based on a fine-grain V_DD control scheme called micro-V_DD-hopping. Four configurable logic blocks (CLBs) are grouped into one block where V_DD is shared. In the micro-V_DD-hopping scheme, V_DD in each block is changed between V_DDH (high V_DD) and V_DDL (low V_DD) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for low-swing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakage-path problem. A test chip was fabricated using a 0.35-µm CMOS technology, together with the conventional fixed-V_DD FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.280/_p

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@ARTICLE{e89-c_3_280,
author={Canh Quang TRAN, Hiroshi KAWAGUCHI, Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping},
year={2006},
volume={E89-C},
number={3},
pages={280-286},
abstract={A low-power FPGA design approach is proposed based on a fine-grain V_DD control scheme called micro-V_DD-hopping. Four configurable logic blocks (CLBs) are grouped into one block where V_DD is shared. In the micro-V_DD-hopping scheme, V_DD in each block is changed between V_DDH (high V_DD) and V_DDL (low V_DD) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for low-swing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakage-path problem. A test chip was fabricated using a 0.35-µm CMOS technology, together with the conventional fixed-V_DD FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%.},
keywords={},
doi={10.1093/ietele/e89-c.3.280},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping
T2 - IEICE TRANSACTIONS on Electronics
SP - 280
EP - 286
AU - Canh Quang TRAN
AU - Hiroshi KAWAGUCHI
AU - Takayasu SAKURAI
PY - 2006
DO - 10.1093/ietele/e89-c.3.280
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - A low-power FPGA design approach is proposed based on a fine-grain V_DD control scheme called micro-V_DD-hopping. Four configurable logic blocks (CLBs) are grouped into one block where V_DD is shared. In the micro-V_DD-hopping scheme, V_DD in each block is changed between V_DDH (high V_DD) and V_DDL (low V_DD) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for low-swing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakage-path problem. A test chip was fabricated using a 0.35-µm CMOS technology, together with the conventional fixed-V_DD FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%.
ER -