A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications

Vahid MAJIDZADEH; Omid SHOAEI

doi:10.1093/ietele/e89-c.6.692

A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications

Vahid MAJIDZADEH, Omid SHOAEI

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A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.692-701

Publication Date: 2006/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.6.692

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)

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Vahid MAJIDZADEH, Omid SHOAEI, "A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 6, pp. 692-701, June 2006, doi: 10.1093/ietele/e89-c.6.692.
Abstract: A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.692/_p

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@ARTICLE{e89-c_6_692,
author={Vahid MAJIDZADEH, Omid SHOAEI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications},
year={2006},
volume={E89-C},
number={6},
pages={692-701},
abstract={A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.},
keywords={},
doi={10.1093/ietele/e89-c.6.692},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 692
EP - 701
AU - Vahid MAJIDZADEH
AU - Omid SHOAEI
PY - 2006
DO - 10.1093/ietele/e89-c.6.692
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.
ER -