A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

Ching-Yuan YANG; Yu LEE; Cheng-Hsing LEE

doi:10.1093/ietele/e89-c.6.746

A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

Ching-Yuan YANG, Yu LEE, Cheng-Hsing LEE

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A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.746-752

Publication Date: 2006/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.6.746

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)

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Ching-Yuan YANG, Yu LEE, Cheng-Hsing LEE, "A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 6, pp. 746-752, June 2006, doi: 10.1093/ietele/e89-c.6.746.
Abstract: A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.746/_p

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@ARTICLE{e89-c_6_746,
author={Ching-Yuan YANG, Yu LEE, Cheng-Hsing LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector},
year={2006},
volume={E89-C},
number={6},
pages={746-752},
abstract={A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.},
keywords={},
doi={10.1093/ietele/e89-c.6.746},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector
T2 - IEICE TRANSACTIONS on Electronics
SP - 746
EP - 752
AU - Ching-Yuan YANG
AU - Yu LEE
AU - Cheng-Hsing LEE
PY - 2006
DO - 10.1093/ietele/e89-c.6.746
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V.
ER -