A Multi-Band Burst-Mode Clock and Data Recovery Circuit

Che-Fu LIANG; Sy-Chyuan HWU; Shen-Iuan LIU

doi:10.1093/ietele/e90-c.4.802

A Multi-Band Burst-Mode Clock and Data Recovery Circuit

Che-Fu LIANG, Sy-Chyuan HWU, Shen-Iuan LIU

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A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm² and consumes 70 mW including I/O buffers from a 1.8 V supply.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.802-810

Publication Date: 2007/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.4.802

Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)

Category: Analog and Communications

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Che-Fu LIANG, Sy-Chyuan HWU, Shen-Iuan LIU, "A Multi-Band Burst-Mode Clock and Data Recovery Circuit" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 4, pp. 802-810, April 2007, doi: 10.1093/ietele/e90-c.4.802.
Abstract: A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm² and consumes 70 mW including I/O buffers from a 1.8 V supply.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.802/_p

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@ARTICLE{e90-c_4_802,
author={Che-Fu LIANG, Sy-Chyuan HWU, Shen-Iuan LIU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Multi-Band Burst-Mode Clock and Data Recovery Circuit},
year={2007},
volume={E90-C},
number={4},
pages={802-810},
abstract={A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm² and consumes 70 mW including I/O buffers from a 1.8 V supply.},
keywords={},
doi={10.1093/ietele/e90-c.4.802},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A Multi-Band Burst-Mode Clock and Data Recovery Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 802
EP - 810
AU - Che-Fu LIANG
AU - Sy-Chyuan HWU
AU - Shen-Iuan LIU
PY - 2007
DO - 10.1093/ietele/e90-c.4.802
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm² and consumes 70 mW including I/O buffers from a 1.8 V supply.
ER -