Technology Mapping Technique for Increasing Throughput of Character Projection Lithography

Makoto SUGIHARA; Kenta NAKAMURA; Yusuke MATSUNAGA; Kazuaki MURAKAMI

doi:10.1093/ietele/e90-c.5.1012

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography

Makoto SUGIHARA, Kenta NAKAMURA, Yusuke MATSUNAGA, Kazuaki MURAKAMI

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The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.5 pp.1012-1020

Publication Date: 2007/05/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.5.1012

Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)

Category: Lithography-Related Techniques

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Makoto SUGIHARA, Kenta NAKAMURA, Yusuke MATSUNAGA, Kazuaki MURAKAMI, "Technology Mapping Technique for Increasing Throughput of Character Projection Lithography" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 5, pp. 1012-1020, May 2007, doi: 10.1093/ietele/e90-c.5.1012.
Abstract: The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.5.1012/_p

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@ARTICLE{e90-c_5_1012,
author={Makoto SUGIHARA, Kenta NAKAMURA, Yusuke MATSUNAGA, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Technology Mapping Technique for Increasing Throughput of Character Projection Lithography},
year={2007},
volume={E90-C},
number={5},
pages={1012-1020},
abstract={The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.},
keywords={},
doi={10.1093/ietele/e90-c.5.1012},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - Technology Mapping Technique for Increasing Throughput of Character Projection Lithography
T2 - IEICE TRANSACTIONS on Electronics
SP - 1012
EP - 1020
AU - Makoto SUGIHARA
AU - Kenta NAKAMURA
AU - Yusuke MATSUNAGA
AU - Kazuaki MURAKAMI
PY - 2007
DO - 10.1093/ietele/e90-c.5.1012
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2007
AB - The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.
ER -