InP HEMT Technology for High-Speed Logic and Communications

Tetsuya SUEMITSU; Masami TOKUMITSU

doi:10.1093/ietele/e90-c.5.917

InP HEMT Technology for High-Speed Logic and Communications

Tetsuya SUEMITSU, Masami TOKUMITSU

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As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.5 pp.917-922

Publication Date: 2007/05/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.5.917

Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)

Category: Compound Semiconductor and Power Devices

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Tetsuya SUEMITSU, Masami TOKUMITSU, "InP HEMT Technology for High-Speed Logic and Communications" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 5, pp. 917-922, May 2007, doi: 10.1093/ietele/e90-c.5.917.
Abstract: As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.5.917/_p

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@ARTICLE{e90-c_5_917,
author={Tetsuya SUEMITSU, Masami TOKUMITSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={InP HEMT Technology for High-Speed Logic and Communications},
year={2007},
volume={E90-C},
number={5},
pages={917-922},
abstract={As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.},
keywords={},
doi={10.1093/ietele/e90-c.5.917},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - InP HEMT Technology for High-Speed Logic and Communications
T2 - IEICE TRANSACTIONS on Electronics
SP - 917
EP - 922
AU - Tetsuya SUEMITSU
AU - Masami TOKUMITSU
PY - 2007
DO - 10.1093/ietele/e90-c.5.917
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2007
AB - As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.
ER -