Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications

O-Sam KWON; Kyeong-Sik MIN

doi:10.1093/ietele/e90-c.7.1540

Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications

O-Sam KWON, Kyeong-Sik MIN

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A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when V_DDL/V_DDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.7 pp.1540-1543

Publication Date: 2007/07/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.7.1540

Type of Manuscript: LETTER

Category: Electronic Circuits

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O-Sam KWON, Kyeong-Sik MIN, "Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 7, pp. 1540-1543, July 2007, doi: 10.1093/ietele/e90-c.7.1540.
Abstract: A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when V_DDL/V_DDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.7.1540/_p

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@ARTICLE{e90-c_7_1540,
author={O-Sam KWON, Kyeong-Sik MIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications},
year={2007},
volume={E90-C},
number={7},
pages={1540-1543},
abstract={A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when V_DDL/V_DDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.},
keywords={},
doi={10.1093/ietele/e90-c.7.1540},
ISSN={1745-1353},
month={July},}

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TY - JOUR
TI - Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 1540
EP - 1543
AU - O-Sam KWON
AU - Kyeong-Sik MIN
PY - 2007
DO - 10.1093/ietele/e90-c.7.1540
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2007
AB - A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when V_DDL/V_DDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.
ER -