Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's

Doo-Hwan KIM; Sung-Hyun YANG; Kyoung-Rok CHO

doi:10.1093/ietele/e91-c.1.72

Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's

Doo-Hwan KIM, Sung-Hyun YANG, Kyoung-Rok CHO

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This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.1 pp.72-80

Publication Date: 2008/01/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.1.72

Type of Manuscript: PAPER

Category: Electronic Circuits

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Doo-Hwan KIM, Sung-Hyun YANG, Kyoung-Rok CHO, "Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 1, pp. 72-80, January 2008, doi: 10.1093/ietele/e91-c.1.72.
Abstract: This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.1.72/_p

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@ARTICLE{e91-c_1_72,
author={Doo-Hwan KIM, Sung-Hyun YANG, Kyoung-Rok CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's},
year={2008},
volume={E91-C},
number={1},
pages={72-80},
abstract={This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.},
keywords={},
doi={10.1093/ietele/e91-c.1.72},
ISSN={1745-1353},
month={January},}

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TY - JOUR
TI - Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's
T2 - IEICE TRANSACTIONS on Electronics
SP - 72
EP - 80
AU - Doo-Hwan KIM
AU - Sung-Hyun YANG
AU - Kyoung-Rok CHO
PY - 2008
DO - 10.1093/ietele/e91-c.1.72
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2008
AB - This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.
ER -