A 10-b 300-MHz Interpolated-Parallel A/D Converter

Hiroshi KIMURA; Akira MATSUZAWA; Takashi NAKAMURA; Shigeki SAWADA

A 10-b 300-MHz Interpolated-Parallel A/D Converter

Hiroshi KIMURA, Akira MATSUZAWA, Takashi NAKAMURA, Shigeki SAWADA

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This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm² chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.5 pp.778-786

Publication Date: 1993/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))

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Hiroshi KIMURA, Akira MATSUZAWA, Takashi NAKAMURA, Shigeki SAWADA, "A 10-b 300-MHz Interpolated-Parallel A/D Converter" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 5, pp. 778-786, May 1993, doi: .
Abstract: This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm² chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e76-c_5_778/_p

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@ARTICLE{e76-c_5_778,
author={Hiroshi KIMURA, Akira MATSUZAWA, Takashi NAKAMURA, Shigeki SAWADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10-b 300-MHz Interpolated-Parallel A/D Converter},
year={1993},
volume={E76-C},
number={5},
pages={778-786},
abstract={This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm² chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A 10-b 300-MHz Interpolated-Parallel A/D Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 778
EP - 786
AU - Hiroshi KIMURA
AU - Akira MATSUZAWA
AU - Takashi NAKAMURA
AU - Shigeki SAWADA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1993
AB - This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm² chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology.
ER -