A Video-Rate 10-b Triple-Stage Bi-CMOS A/D Converter

Akira MATSUZAWA; Shoichiro TADA

A Video-Rate 10-b Triple-Stage Bi-CMOS A/D Converter

Akira MATSUZAWA, Shoichiro TADA

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This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm² and consumes 350 mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.12 pp.1903-1911

Publication Date: 1994/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)

Category: Analog LSIs

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Akira MATSUZAWA, Shoichiro TADA, "A Video-Rate 10-b Triple-Stage Bi-CMOS A/D Converter" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 12, pp. 1903-1911, December 1994, doi: .
Abstract: This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm² and consumes 350 mW.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_12_1903/_p

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@ARTICLE{e77-c_12_1903,
author={Akira MATSUZAWA, Shoichiro TADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Video-Rate 10-b Triple-Stage Bi-CMOS A/D Converter},
year={1994},
volume={E77-C},
number={12},
pages={1903-1911},
abstract={This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm² and consumes 350 mW.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Video-Rate 10-b Triple-Stage Bi-CMOS A/D Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 1903
EP - 1911
AU - Akira MATSUZAWA
AU - Shoichiro TADA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1994
AB - This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm² and consumes 350 mW.
ER -