High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application

Masao TAGUCHI

High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application

Masao TAGUCHI

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High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.12 pp.1944-1950

Publication Date: 1994/12/25

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on Multimedia, Analog and Processing LSIs)

Category: Processor Interfaces

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Masao TAGUCHI, "High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 12, pp. 1944-1950, December 1994, doi: .
Abstract: High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_12_1944/_p

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@ARTICLE{e77-c_12_1944,
author={Masao TAGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application},
year={1994},
volume={E77-C},
number={12},
pages={1944-1950},
abstract={High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 1944
EP - 1950
AU - Masao TAGUCHI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1994
AB - High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.
ER -