A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.
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Norio KUJI, Kiyoshi MATSUMOTO, "E-Beam Static Fault Imaging with a CAD Interface and Its Application to Marginal Fault Diagnosis" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 4, pp. 552-559, April 1994, doi: .
Abstract: A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_4_552/_p
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@ARTICLE{e77-c_4_552,
author={Norio KUJI, Kiyoshi MATSUMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={E-Beam Static Fault Imaging with a CAD Interface and Its Application to Marginal Fault Diagnosis},
year={1994},
volume={E77-C},
number={4},
pages={552-559},
abstract={A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - E-Beam Static Fault Imaging with a CAD Interface and Its Application to Marginal Fault Diagnosis
T2 - IEICE TRANSACTIONS on Electronics
SP - 552
EP - 559
AU - Norio KUJI
AU - Kiyoshi MATSUMOTO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1994
AB - A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.
ER -