Quantizer Neuron Chip (QNC) with Multichip Extendable Architecture

Masakatsu MARUYAMA; Hiroyuki NAKAHIRA; Shiro SAKIYAMA; Toshiyuki KOHDA; Susumu MARUNO; Yasuharu SHIMEKI

Quantizer Neuron Chip (QNC) with Multichip Extendable Architecture

Masakatsu MARUYAMA, Hiroyuki NAKAHIRA, Shiro SAKIYAMA, Toshiyuki KOHDA, Susumu MARUNO, Yasuharu SHIMEKI

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This paper discusses a digital neuroprocessor named Quantizer Neuron Chip (QNC) employing the Quantizer Neuron model and two newly developed schemes; "concurrent processing of quantizer neuron" and "removal of ineffective calculations". QNC simulates neural networks named the Multi-Functional Layered Network (MFLN) with 64 output neurons, 4672 quantizer neurons and two million synaptic weights and can be used for character or image recognition and learning. The processing speed of the chip achieved 1.6 µseconds per output neuron for recognition and 20 million connections updated per second (MCUPS) for learning. In addition, QNC can execute multichip operation for increasing the size of networks. We applied QNC to handwritten numeral recognition and realized high speed recognition and learning. QNC is implemented in a 1.2 µm double metal CMOS with sea of gates' technology and contains 27,000 gates on a 10.9910.93 mm² chip.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.7 pp.1057-1064

Publication Date: 1994/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)

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Masakatsu MARUYAMA, Hiroyuki NAKAHIRA, Shiro SAKIYAMA, Toshiyuki KOHDA, Susumu MARUNO, Yasuharu SHIMEKI, "Quantizer Neuron Chip (QNC) with Multichip Extendable Architecture" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 7, pp. 1057-1064, July 1994, doi: .
Abstract: This paper discusses a digital neuroprocessor named Quantizer Neuron Chip (QNC) employing the Quantizer Neuron model and two newly developed schemes; "concurrent processing of quantizer neuron" and "removal of ineffective calculations". QNC simulates neural networks named the Multi-Functional Layered Network (MFLN) with 64 output neurons, 4672 quantizer neurons and two million synaptic weights and can be used for character or image recognition and learning. The processing speed of the chip achieved 1.6 µseconds per output neuron for recognition and 20 million connections updated per second (MCUPS) for learning. In addition, QNC can execute multichip operation for increasing the size of networks. We applied QNC to handwritten numeral recognition and realized high speed recognition and learning. QNC is implemented in a 1.2 µm double metal CMOS with sea of gates' technology and contains 27,000 gates on a 10.9910.93 mm² chip.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_7_1057/_p

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@ARTICLE{e77-c_7_1057,
author={Masakatsu MARUYAMA, Hiroyuki NAKAHIRA, Shiro SAKIYAMA, Toshiyuki KOHDA, Susumu MARUNO, Yasuharu SHIMEKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Quantizer Neuron Chip (QNC) with Multichip Extendable Architecture},
year={1994},
volume={E77-C},
number={7},
pages={1057-1064},
abstract={This paper discusses a digital neuroprocessor named Quantizer Neuron Chip (QNC) employing the Quantizer Neuron model and two newly developed schemes; "concurrent processing of quantizer neuron" and "removal of ineffective calculations". QNC simulates neural networks named the Multi-Functional Layered Network (MFLN) with 64 output neurons, 4672 quantizer neurons and two million synaptic weights and can be used for character or image recognition and learning. The processing speed of the chip achieved 1.6 µseconds per output neuron for recognition and 20 million connections updated per second (MCUPS) for learning. In addition, QNC can execute multichip operation for increasing the size of networks. We applied QNC to handwritten numeral recognition and realized high speed recognition and learning. QNC is implemented in a 1.2 µm double metal CMOS with sea of gates' technology and contains 27,000 gates on a 10.9910.93 mm² chip.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Quantizer Neuron Chip (QNC) with Multichip Extendable Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1057
EP - 1064
AU - Masakatsu MARUYAMA
AU - Hiroyuki NAKAHIRA
AU - Shiro SAKIYAMA
AU - Toshiyuki KOHDA
AU - Susumu MARUNO
AU - Yasuharu SHIMEKI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1994
AB - This paper discusses a digital neuroprocessor named Quantizer Neuron Chip (QNC) employing the Quantizer Neuron model and two newly developed schemes; "concurrent processing of quantizer neuron" and "removal of ineffective calculations". QNC simulates neural networks named the Multi-Functional Layered Network (MFLN) with 64 output neurons, 4672 quantizer neurons and two million synaptic weights and can be used for character or image recognition and learning. The processing speed of the chip achieved 1.6 µseconds per output neuron for recognition and 20 million connections updated per second (MCUPS) for learning. In addition, QNC can execute multichip operation for increasing the size of networks. We applied QNC to handwritten numeral recognition and realized high speed recognition and learning. QNC is implemented in a 1.2 µm double metal CMOS with sea of gates' technology and contains 27,000 gates on a 10.9910.93 mm² chip.
ER -