A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme

Hisashi IWAMOTO; Naoya WATANABE; Akira YAMAZAKI; Seiji SAWADA; Yasumitsu MURAI; Yasuhiro KONISHI; Hiroshi ITOH; Masaki KUMANOYA

A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme

Hisashi IWAMOTO, Naoya WATANABE, Akira YAMAZAKI, Seiji SAWADA, Yasumitsu MURAI, Yasuhiro KONISHI, Hiroshi ITOH, Masaki KUMANOYA

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A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.8 pp.1328-1333

Publication Date: 1994/08/25

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Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)

Category: DRAM

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Hisashi IWAMOTO, Naoya WATANABE, Akira YAMAZAKI, Seiji SAWADA, Yasumitsu MURAI, Yasuhiro KONISHI, Hiroshi ITOH, Masaki KUMANOYA, "A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 8, pp. 1328-1333, August 1994, doi: .
Abstract: A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_8_1328/_p

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@ARTICLE{e77-c_8_1328,
author={Hisashi IWAMOTO, Naoya WATANABE, Akira YAMAZAKI, Seiji SAWADA, Yasumitsu MURAI, Yasuhiro KONISHI, Hiroshi ITOH, Masaki KUMANOYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme},
year={1994},
volume={E77-C},
number={8},
pages={1328-1333},
abstract={A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 1328
EP - 1333
AU - Hisashi IWAMOTO
AU - Naoya WATANABE
AU - Akira YAMAZAKI
AU - Seiji SAWADA
AU - Yasumitsu MURAI
AU - Yasuhiro KONISHI
AU - Hiroshi ITOH
AU - Masaki KUMANOYA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1994
AB - A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.
ER -