Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System

Katsuyoshi MIURA; Koji NAKAMAE; hiromu FUJIOKA

Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System

Katsuyoshi MIURA, Koji NAKAMAE, hiromu FUJIOKA

Full Text Views

0

Share
Cite this

Summary :

An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.11 pp.1607-1617

Publication Date: 1995/11/25

Publicized

Online ISSN

DOI

Type of Manuscript: PAPER

Category: Integrated Electronics

Cite this

Copy

Katsuyoshi MIURA, Koji NAKAMAE, hiromu FUJIOKA, "Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 11, pp. 1607-1617, November 1995, doi: .
Abstract: An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_11_1607/_p

Copy

@ARTICLE{e78-c_11_1607,
author={Katsuyoshi MIURA, Koji NAKAMAE, hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System},
year={1995},
volume={E78-C},
number={11},
pages={1607-1617},
abstract={An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.},
keywords={},
doi={},
ISSN={},
month={November},}

Copy

TY - JOUR
TI - Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System
T2 - IEICE TRANSACTIONS on Electronics
SP - 1607
EP - 1617
AU - Katsuyoshi MIURA
AU - Koji NAKAMAE
AU - hiromu FUJIOKA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1995
AB - An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.
ER -