A Distributed BIST Technique and Its Test Design Platrorm for VLSIs

Takeshi IKENAGA; Takeshi OGURA

A Distributed BIST Technique and Its Test Design Platrorm for VLSIs

Takeshi IKENAGA, Takeshi OGURA

Full Text Views

0

Share
Cite this

Summary :

This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.11 pp.1618-1623

Publication Date: 1995/11/25

Publicized

Online ISSN

DOI

Type of Manuscript: PAPER

Category: Integrated Electronics

Cite this

Copy

Takeshi IKENAGA, Takeshi OGURA, "A Distributed BIST Technique and Its Test Design Platrorm for VLSIs" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 11, pp. 1618-1623, November 1995, doi: .
Abstract: This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_11_1618/_p

Copy

@ARTICLE{e78-c_11_1618,
author={Takeshi IKENAGA, Takeshi OGURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Distributed BIST Technique and Its Test Design Platrorm for VLSIs},
year={1995},
volume={E78-C},
number={11},
pages={1618-1623},
abstract={This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.},
keywords={},
doi={},
ISSN={},
month={November},}

Copy

TY - JOUR
TI - A Distributed BIST Technique and Its Test Design Platrorm for VLSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1618
EP - 1623
AU - Takeshi IKENAGA
AU - Takeshi OGURA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1995
AB - This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.
ER -