Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement

Hideyuki FUKUHARA; Takao KOMATSUZAKI; Katsushi BOKU; Yoichi MIYAI

Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement

Hideyuki FUKUHARA, Takao KOMATSUZAKI, Katsushi BOKU, Yoichi MIYAI

Full Text Views

0

Share
Cite this

Summary :

There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.852-857

Publication Date: 1995/07/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)

Category

Cite this

Copy

Hideyuki FUKUHARA, Takao KOMATSUZAKI, Katsushi BOKU, Yoichi MIYAI, "Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 7, pp. 852-857, July 1995, doi: .
Abstract: There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_7_852/_p

Copy

@ARTICLE{e78-c_7_852,
author={Hideyuki FUKUHARA, Takao KOMATSUZAKI, Katsushi BOKU, Yoichi MIYAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement},
year={1995},
volume={E78-C},
number={7},
pages={852-857},
abstract={There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.},
keywords={},
doi={},
ISSN={},
month={July},}

Copy

TY - JOUR
TI - Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement
T2 - IEICE TRANSACTIONS on Electronics
SP - 852
EP - 857
AU - Hideyuki FUKUHARA
AU - Takao KOMATSUZAKI
AU - Katsushi BOKU
AU - Yoichi MIYAI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.
ER -