Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array

Yoji NISHIO; Hideo HARA; Masahiro IWAMURA; Yasuo KAMINAGA; Katsunori KOIKE; Kosaku HIROSE; Takayuki NOTO; Satoshi OGUCHI; Yoshihiko YAMAMOTO; Takeshi ONO

Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array

Yoji NISHIO, Hideo HARA, Masahiro IWAMURA, Yasuo KAMINAGA, Katsunori KOIKE, Kosaku HIROSE, Takayuki NOTO, Satoshi OGUCHI, Yoshihiko YAMAMOTO, Takeshi ONO

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A 0.5 µm CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell; high speed, compiled type metallized and diffused RAMs; PLL (Phase Locked Loop); and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.9 pp.1255-1262

Publication Date: 1995/09/25

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Yoji NISHIO, Hideo HARA, Masahiro IWAMURA, Yasuo KAMINAGA, Katsunori KOIKE, Kosaku HIROSE, Takayuki NOTO, Satoshi OGUCHI, Yoshihiko YAMAMOTO, Takeshi ONO, "Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 9, pp. 1255-1262, September 1995, doi: .
Abstract: A 0.5 µm CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell; high speed, compiled type metallized and diffused RAMs; PLL (Phase Locked Loop); and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_9_1255/_p

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@ARTICLE{e78-c_9_1255,
author={Yoji NISHIO, Hideo HARA, Masahiro IWAMURA, Yasuo KAMINAGA, Katsunori KOIKE, Kosaku HIROSE, Takayuki NOTO, Satoshi OGUCHI, Yoshihiko YAMAMOTO, Takeshi ONO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array},
year={1995},
volume={E78-C},
number={9},
pages={1255-1262},
abstract={A 0.5 µm CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell; high speed, compiled type metallized and diffused RAMs; PLL (Phase Locked Loop); and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array
T2 - IEICE TRANSACTIONS on Electronics
SP - 1255
EP - 1262
AU - Yoji NISHIO
AU - Hideo HARA
AU - Masahiro IWAMURA
AU - Yasuo KAMINAGA
AU - Katsunori KOIKE
AU - Kosaku HIROSE
AU - Takayuki NOTO
AU - Satoshi OGUCHI
AU - Yoshihiko YAMAMOTO
AU - Takeshi ONO
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1995
AB - A 0.5 µm CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell; high speed, compiled type metallized and diffused RAMs; PLL (Phase Locked Loop); and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.
ER -