SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories

Shigehiro KUGE; Fukashi MORISHITA; Takahiro TSURUDA; Shigeki TOMISHIMA; Masaki TSUKUDE; Tadato YAMAGATA; Kazutami ARIMOTO

SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories

Shigehiro KUGE, Fukashi MORISHITA, Takahiro TSURUDA, Shigeki TOMISHIMA, Masaki TSUKUDE, Tadato YAMAGATA, Kazutami ARIMOTO

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This parer describes a silicon on insulator(SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline Short is also discussed in respect of yield and area penalty.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.7 pp.997-1002

Publication Date: 1996/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))

Category: Memory

Authors

Shigehiro KUGE
Fukashi MORISHITA
Takahiro TSURUDA
Shigeki TOMISHIMA
Masaki TSUKUDE
Tadato YAMAGATA
Kazutami ARIMOTO

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Shigehiro KUGE, Fukashi MORISHITA, Takahiro TSURUDA, Shigeki TOMISHIMA, Masaki TSUKUDE, Tadato YAMAGATA, Kazutami ARIMOTO, "SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 7, pp. 997-1002, July 1996, doi: .
Abstract: This parer describes a silicon on insulator(SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline Short is also discussed in respect of yield and area penalty.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_7_997/_p

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@ARTICLE{e79-c_7_997,
author={Shigehiro KUGE, Fukashi MORISHITA, Takahiro TSURUDA, Shigeki TOMISHIMA, Masaki TSUKUDE, Tadato YAMAGATA, Kazutami ARIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories},
year={1996},
volume={E79-C},
number={7},
pages={997-1002},
abstract={This parer describes a silicon on insulator(SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline Short is also discussed in respect of yield and area penalty.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 997
EP - 1002
AU - Shigehiro KUGE
AU - Fukashi MORISHITA
AU - Takahiro TSURUDA
AU - Shigeki TOMISHIMA
AU - Masaki TSUKUDE
AU - Tadato YAMAGATA
AU - Kazutami ARIMOTO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1996
AB - This parer describes a silicon on insulator(SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline Short is also discussed in respect of yield and area penalty.
ER -