Regenerative Pass-Transistor Logic:  A Circuit Technique for High Speed Digital Design

Tsz Shing CHEUNG; Kunihiro ASADA

Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design

Tsz Shing CHEUNG, Kunihiro ASADA

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Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.9 pp.1274-1284

Publication Date: 1996/09/25

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Tsz Shing CHEUNG, Kunihiro ASADA, "Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 9, pp. 1274-1284, September 1996, doi: .
Abstract: Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e79-c_9_1274/_p

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@ARTICLE{e79-c_9_1274,
author={Tsz Shing CHEUNG, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design},
year={1996},
volume={E79-C},
number={9},
pages={1274-1284},
abstract={Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 1274
EP - 1284
AU - Tsz Shing CHEUNG
AU - Kunihiro ASADA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1996
AB - Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.
ER -