Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System

Katsuyoshi MIURA; Koji NAKAMAE; Hiromu FUJIOKA

Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System

Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA

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A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.3 pp.498-502

Publication Date: 1997/03/25

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Category: Integrated Electronics

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Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA, "Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 3, pp. 498-502, March 1997, doi: .
Abstract: A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e80-c_3_498/_p

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@ARTICLE{e80-c_3_498,
author={Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System},
year={1997},
volume={E80-C},
number={3},
pages={498-502},
abstract={A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System
T2 - IEICE TRANSACTIONS on Electronics
SP - 498
EP - 502
AU - Katsuyoshi MIURA
AU - Koji NAKAMAE
AU - Hiromu FUJIOKA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1997
AB - A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.
ER -