Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic

Minkyu SONG; Kunihiro ASADA

Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic

Minkyu SONG, Kunihiro ASADA

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In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E81-C No.11 pp.1740-1749

Publication Date: 1998/11/25

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Category: Integrated Electronics

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Minkyu SONG, Kunihiro ASADA, "Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic" in IEICE TRANSACTIONS on Electronics, vol. E81-C, no. 11, pp. 1740-1749, November 1998, doi: .
Abstract: In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e81-c_11_1740/_p

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@ARTICLE{e81-c_11_1740,
author={Minkyu SONG, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic},
year={1998},
volume={E81-C},
number={11},
pages={1740-1749},
abstract={In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 1740
EP - 1749
AU - Minkyu SONG
AU - Kunihiro ASADA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1998
AB - In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.
ER -