Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro

Kenichi OHHATA; Takeshi KUSUNOKI; Hiroaki NAMBU; Kazuo KANETANI; Keiichi HIGETA; Kunihiko YAMAGUCHI; Noriyuki HOMMA

Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro

Kenichi OHHATA, Takeshi KUSUNOKI, Hiroaki NAMBU, Kazuo KANETANI, Keiichi HIGETA, Kunihiko YAMAGUCHI, Noriyuki HOMMA

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We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.

Publication: IEICE TRANSACTIONS on Electronics Vol.E81-C No.3 pp.447-454

Publication Date: 1998/03/25

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Category: Integrated Electronics

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Kenichi OHHATA, Takeshi KUSUNOKI, Hiroaki NAMBU, Kazuo KANETANI, Keiichi HIGETA, Kunihiko YAMAGUCHI, Noriyuki HOMMA, "Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro" in IEICE TRANSACTIONS on Electronics, vol. E81-C, no. 3, pp. 447-454, March 1998, doi: .
Abstract: We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e81-c_3_447/_p

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@ARTICLE{e81-c_3_447,
author={Kenichi OHHATA, Takeshi KUSUNOKI, Hiroaki NAMBU, Kazuo KANETANI, Keiichi HIGETA, Kunihiko YAMAGUCHI, Noriyuki HOMMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro},
year={1998},
volume={E81-C},
number={3},
pages={447-454},
abstract={We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro
T2 - IEICE TRANSACTIONS on Electronics
SP - 447
EP - 454
AU - Kenichi OHHATA
AU - Takeshi KUSUNOKI
AU - Hiroaki NAMBU
AU - Kazuo KANETANI
AU - Keiichi HIGETA
AU - Kunihiko YAMAGUCHI
AU - Noriyuki HOMMA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1998
AB - We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.
ER -