A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free

Sung-Hyun YANG; Younggap YOU; Kyoung-Rok CHO

A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free

Sung-Hyun YANG, Younggap YOU, Kyoung-Rok CHO

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A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E86-C No.3 pp.496-505

Publication Date: 2003/03/01

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Type of Manuscript: PAPER

Category: Electronic Circuits

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Sung-Hyun YANG, Younggap YOU, Kyoung-Rok CHO, "A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free" in IEICE TRANSACTIONS on Electronics, vol. E86-C, no. 3, pp. 496-505, March 2003, doi: .
Abstract: A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e86-c_3_496/_p

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@ARTICLE{e86-c_3_496,
author={Sung-Hyun YANG, Younggap YOU, Kyoung-Rok CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free},
year={2003},
volume={E86-C},
number={3},
pages={496-505},
abstract={A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free
T2 - IEICE TRANSACTIONS on Electronics
SP - 496
EP - 505
AU - Sung-Hyun YANG
AU - Younggap YOU
AU - Kyoung-Rok CHO
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2003
AB - A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.
ER -