Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture

Masanori HARIYAMA; Weisheng CHONG; Michitaka KAMEYAMA

Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture

Masanori HARIYAMA, Weisheng CHONG, Michitaka KAMEYAMA

Full Text Views

0

Share
Cite this

Summary :

This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.11 pp.1897-1902

Publication Date: 2004/11/01

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)

Category

Cite this

Copy

Masanori HARIYAMA, Weisheng CHONG, Michitaka KAMEYAMA, "Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 11, pp. 1897-1902, November 2004, doi: .
Abstract: This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_11_1897/_p

Copy

@ARTICLE{e87-c_11_1897,
author={Masanori HARIYAMA, Weisheng CHONG, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture},
year={2004},
volume={E87-C},
number={11},
pages={1897-1902},
abstract={This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.},
keywords={},
doi={},
ISSN={},
month={November},}

Copy

TY - JOUR
TI - Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1897
EP - 1902
AU - Masanori HARIYAMA
AU - Weisheng CHONG
AU - Michitaka KAMEYAMA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2004
AB - This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.
ER -