A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation

Kentaro NAGAI; Jun SHIOMI; Hidetoshi ONODERA

doi:10.1587/transele.2020CTP0002

A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation

Kentaro NAGAI, Jun SHIOMI, Hidetoshi ONODERA

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This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E104-C No.10 pp.617-624

Publication Date: 2021/10/01

Publicized: 2021/04/20

Online ISSN: 1745-1353

DOI: 10.1587/transele.2020CTP0002

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)

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Authors

Kentaro NAGAI
  Kyoto University
Jun SHIOMI
  Kyoto University
Hidetoshi ONODERA
  Kyoto University

Keyword

body bias generator, minimum energy point tracking (MEPT), adaptive body bias (ABB), analog-assisted digital

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Kentaro NAGAI, Jun SHIOMI, Hidetoshi ONODERA, "A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation" in IEICE TRANSACTIONS on Electronics, vol. E104-C, no. 10, pp. 617-624, October 2021, doi: 10.1587/transele.2020CTP0002.
Abstract: This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.2020CTP0002/_p

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@ARTICLE{e104-c_10_617,
author={Kentaro NAGAI, Jun SHIOMI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation},
year={2021},
volume={E104-C},
number={10},
pages={617-624},
abstract={This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.},
keywords={},
doi={10.1587/transele.2020CTP0002},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 617
EP - 624
AU - Kentaro NAGAI
AU - Jun SHIOMI
AU - Hidetoshi ONODERA
PY - 2021
DO - 10.1587/transele.2020CTP0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2021
AB - This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.
ER -