Applying Razor Flip-Flops to SRAM Read Circuits

Ushio JIMBO; Junji YAMADA; Ryota SHIOYA; Masahiro GOSHIMA

doi:10.1587/transele.E100.C.245

Applying Razor Flip-Flops to SRAM Read Circuits

Ushio JIMBO, Junji YAMADA, Ryota SHIOYA, Masahiro GOSHIMA

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Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). The Razor flip-flop (FF) is a timing fault detection technique that employs double sampling by the main and shadow FFs. In order for the Razor FF to correctly detect a timing fault, not the main FF but the shadow FF must sample the correct value. The application of Razor FFs to static logic relaxes the timing constraints; however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. This is because the SRAM precharge cannot start before the shadow FF samples the value; otherwise, the transition of the bitline of the SRAM stops and the value sampled by the shadow FF will be incorrect. Therefore, the detect period cannot overlap the precharge period. This paper proposes a novel application of Razor FFs to SRAM read circuits. Our proposal employs a conditional precharge according to the value of a bitline sampled by the main FF. This enables the detect period to overlap the precharge period, thereby relaxing the timing constraints. The additional circuit required by this method is simple and only needed around the sense amplifier, and there is no need for a clock delayed from the system clock. Consequently, the area overhead of the proposed circuit is negligible. This paper presents SPICE simulations of the proposed circuit. Our proposal reduces the minimum cycle time by 51.5% at a supply voltage of 1.1 V and the minimum voltage by 31.8% at cycle time of 412.5 ps.

Publication: IEICE TRANSACTIONS on Electronics Vol.E100-C No.3 pp.245-258

Publication Date: 2017/03/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E100.C.245

Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)

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Authors

Ushio JIMBO
  SOKENDAI (The Graduate University for Advanced Studies)
Junji YAMADA
  The University of Tokyo
Ryota SHIOYA
  Nagoya University
Masahiro GOSHIMA
  National Institute of Informatics

Keyword

random variation, timing fault detection and recovery, dynamic voltage and frequency scaling (DVFS), SRAM

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Ushio JIMBO, Junji YAMADA, Ryota SHIOYA, Masahiro GOSHIMA, "Applying Razor Flip-Flops to SRAM Read Circuits" in IEICE TRANSACTIONS on Electronics, vol. E100-C, no. 3, pp. 245-258, March 2017, doi: 10.1587/transele.E100.C.245.
Abstract: Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). The Razor flip-flop (FF) is a timing fault detection technique that employs double sampling by the main and shadow FFs. In order for the Razor FF to correctly detect a timing fault, not the main FF but the shadow FF must sample the correct value. The application of Razor FFs to static logic relaxes the timing constraints; however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. This is because the SRAM precharge cannot start before the shadow FF samples the value; otherwise, the transition of the bitline of the SRAM stops and the value sampled by the shadow FF will be incorrect. Therefore, the detect period cannot overlap the precharge period. This paper proposes a novel application of Razor FFs to SRAM read circuits. Our proposal employs a conditional precharge according to the value of a bitline sampled by the main FF. This enables the detect period to overlap the precharge period, thereby relaxing the timing constraints. The additional circuit required by this method is simple and only needed around the sense amplifier, and there is no need for a clock delayed from the system clock. Consequently, the area overhead of the proposed circuit is negligible. This paper presents SPICE simulations of the proposed circuit. Our proposal reduces the minimum cycle time by 51.5% at a supply voltage of 1.1 V and the minimum voltage by 31.8% at cycle time of 412.5 ps.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.245/_p

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@ARTICLE{e100-c_3_245,
author={Ushio JIMBO, Junji YAMADA, Ryota SHIOYA, Masahiro GOSHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Applying Razor Flip-Flops to SRAM Read Circuits},
year={2017},
volume={E100-C},
number={3},
pages={245-258},
abstract={Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). The Razor flip-flop (FF) is a timing fault detection technique that employs double sampling by the main and shadow FFs. In order for the Razor FF to correctly detect a timing fault, not the main FF but the shadow FF must sample the correct value. The application of Razor FFs to static logic relaxes the timing constraints; however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. This is because the SRAM precharge cannot start before the shadow FF samples the value; otherwise, the transition of the bitline of the SRAM stops and the value sampled by the shadow FF will be incorrect. Therefore, the detect period cannot overlap the precharge period. This paper proposes a novel application of Razor FFs to SRAM read circuits. Our proposal employs a conditional precharge according to the value of a bitline sampled by the main FF. This enables the detect period to overlap the precharge period, thereby relaxing the timing constraints. The additional circuit required by this method is simple and only needed around the sense amplifier, and there is no need for a clock delayed from the system clock. Consequently, the area overhead of the proposed circuit is negligible. This paper presents SPICE simulations of the proposed circuit. Our proposal reduces the minimum cycle time by 51.5% at a supply voltage of 1.1 V and the minimum voltage by 31.8% at cycle time of 412.5 ps.},
keywords={},
doi={10.1587/transele.E100.C.245},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - Applying Razor Flip-Flops to SRAM Read Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 245
EP - 258
AU - Ushio JIMBO
AU - Junji YAMADA
AU - Ryota SHIOYA
AU - Masahiro GOSHIMA
PY - 2017
DO - 10.1587/transele.E100.C.245
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2017
AB - Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). The Razor flip-flop (FF) is a timing fault detection technique that employs double sampling by the main and shadow FFs. In order for the Razor FF to correctly detect a timing fault, not the main FF but the shadow FF must sample the correct value. The application of Razor FFs to static logic relaxes the timing constraints; however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. This is because the SRAM precharge cannot start before the shadow FF samples the value; otherwise, the transition of the bitline of the SRAM stops and the value sampled by the shadow FF will be incorrect. Therefore, the detect period cannot overlap the precharge period. This paper proposes a novel application of Razor FFs to SRAM read circuits. Our proposal employs a conditional precharge according to the value of a bitline sampled by the main FF. This enables the detect period to overlap the precharge period, thereby relaxing the timing constraints. The additional circuit required by this method is simple and only needed around the sense amplifier, and there is no need for a clock delayed from the system clock. Consequently, the area overhead of the proposed circuit is negligible. This paper presents SPICE simulations of the proposed circuit. Our proposal reduces the minimum cycle time by 51.5% at a supply voltage of 1.1 V and the minimum voltage by 31.8% at cycle time of 412.5 ps.
ER -