A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI

Aravind THARAYIL NARAYANAN; Wei DENG; Dongsheng YANG; Rui WU; Kenichi OKADA; Akira MATSUZAWA

doi:10.1587/transele.E100.C.259

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI

Aravind THARAYIL NARAYANAN, Wei DENG, Dongsheng YANG, Rui WU, Kenichi OKADA, Akira MATSUZAWA

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An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.

Publication: IEICE TRANSACTIONS on Electronics Vol.E100-C No.3 pp.259-267

Publication Date: 2017/03/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E100.C.259

Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)

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Authors

Aravind THARAYIL NARAYANAN
  Tokyo Institute of Technology
Wei DENG
  Apple Inc.
Dongsheng YANG
  Tokyo Institute of Technology
Rui WU
  Tokyo Institute of Technology
Kenichi OKADA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

fully-synthesizable, all-digital, clock data recovery, injection locking, phase-filtering

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Aravind THARAYIL NARAYANAN, Wei DENG, Dongsheng YANG, Rui WU, Kenichi OKADA, Akira MATSUZAWA, "A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI" in IEICE TRANSACTIONS on Electronics, vol. E100-C, no. 3, pp. 259-267, March 2017, doi: 10.1587/transele.E100.C.259.
Abstract: An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.259/_p

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@ARTICLE{e100-c_3_259,
author={Aravind THARAYIL NARAYANAN, Wei DENG, Dongsheng YANG, Rui WU, Kenichi OKADA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI},
year={2017},
volume={E100-C},
number={3},
pages={259-267},
abstract={An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.},
keywords={},
doi={10.1587/transele.E100.C.259},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI
T2 - IEICE TRANSACTIONS on Electronics
SP - 259
EP - 267
AU - Aravind THARAYIL NARAYANAN
AU - Wei DENG
AU - Dongsheng YANG
AU - Rui WU
AU - Kenichi OKADA
AU - Akira MATSUZAWA
PY - 2017
DO - 10.1587/transele.E100.C.259
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2017
AB - An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.
ER -