Highly Robust Double Node Upset Resilient Hardened Latch Design

Huaguo LIANG; Xin LI; Zhengfeng HUANG; Aibin YAN; Xiumin XU

doi:10.1587/transele.E100.C.496

Highly Robust Double Node Upset Resilient Hardened Latch Design

Huaguo LIANG, Xin LI, Zhengfeng HUANG, Aibin YAN, Xiumin XU

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Summary :

With the scaling of technology, nanoscale CMOS integrated circuits are becoming more sensitive to single event double node upsets induced by charge sharing. A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.

Publication: IEICE TRANSACTIONS on Electronics Vol.E100-C No.5 pp.496-503

Publication Date: 2017/05/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E100.C.496

Type of Manuscript: PAPER

Category: Electronic Circuits

Authors

Huaguo LIANG
  Hefei University of Technology
Xin LI
  Hefei University of Technology
Zhengfeng HUANG
  Hefei University of Technology
Aibin YAN
  Anhui University
Xiumin XU
  Hefei University of Technology

Keyword

single event double node upset, single node upset, resilience, radiation hardened latch

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Huaguo LIANG, Xin LI, Zhengfeng HUANG, Aibin YAN, Xiumin XU, "Highly Robust Double Node Upset Resilient Hardened Latch Design" in IEICE TRANSACTIONS on Electronics, vol. E100-C, no. 5, pp. 496-503, May 2017, doi: 10.1587/transele.E100.C.496.
Abstract: With the scaling of technology, nanoscale CMOS integrated circuits are becoming more sensitive to single event double node upsets induced by charge sharing. A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.496/_p

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@ARTICLE{e100-c_5_496,
author={Huaguo LIANG, Xin LI, Zhengfeng HUANG, Aibin YAN, Xiumin XU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Highly Robust Double Node Upset Resilient Hardened Latch Design},
year={2017},
volume={E100-C},
number={5},
pages={496-503},
abstract={With the scaling of technology, nanoscale CMOS integrated circuits are becoming more sensitive to single event double node upsets induced by charge sharing. A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.},
keywords={},
doi={10.1587/transele.E100.C.496},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - Highly Robust Double Node Upset Resilient Hardened Latch Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 496
EP - 503
AU - Huaguo LIANG
AU - Xin LI
AU - Zhengfeng HUANG
AU - Aibin YAN
AU - Xiumin XU
PY - 2017
DO - 10.1587/transele.E100.C.496
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2017
AB - With the scaling of technology, nanoscale CMOS integrated circuits are becoming more sensitive to single event double node upsets induced by charge sharing. A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.
ER -