On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement

Masaaki SODA; Yoji BANDO; Satoshi TAKAYA; Toru OHKAWA; Toshiharu TAKARAMOTO; Toshio YAMADA; Shigetaka KUMASHIRO; Tohru MOGAMI; Makoto NAGATA

doi:10.1587/transele.E94.C.1024

On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement

Masaaki SODA, Yoji BANDO, Satoshi TAKAYA, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA

Full Text Views

0

Share
Cite this

Summary :

A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with 1 MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.6 pp.1024-1031

Publication Date: 2011/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.1024

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

Category

Cite this

Copy

Masaaki SODA, Yoji BANDO, Satoshi TAKAYA, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA, "On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 6, pp. 1024-1031, June 2011, doi: 10.1587/transele.E94.C.1024.
Abstract: A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with 1 MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1024/_p

Copy

@ARTICLE{e94-c_6_1024,
author={Masaaki SODA, Yoji BANDO, Satoshi TAKAYA, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement},
year={2011},
volume={E94-C},
number={6},
pages={1024-1031},
abstract={A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with 1 MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.},
keywords={},
doi={10.1587/transele.E94.C.1024},
ISSN={1745-1353},
month={June},}

Copy

TY - JOUR
TI - On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
T2 - IEICE TRANSACTIONS on Electronics
SP - 1024
EP - 1031
AU - Masaaki SODA
AU - Yoji BANDO
AU - Satoshi TAKAYA
AU - Toru OHKAWA
AU - Toshiharu TAKARAMOTO
AU - Toshio YAMADA
AU - Shigetaka KUMASHIRO
AU - Tohru MOGAMI
AU - Makoto NAGATA
PY - 2011
DO - 10.1587/transele.E94.C.1024
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with 1 MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.
ER -