Study on Address Discharge Characteristics by Changing Ramp-Down Voltage in AC PDPs

Joon-Yub KIM; Yeon Tae JEONG; Byung-Gwon CHO

doi:10.1587/transele.E94.C.1483

Study on Address Discharge Characteristics by Changing Ramp-Down Voltage in AC PDPs

Joon-Yub KIM, Yeon Tae JEONG, Byung-Gwon CHO

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The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.9 pp.1483-1485

Publication Date: 2011/09/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.1483

Type of Manuscript: BRIEF PAPER

Category: Electronic Displays

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Joon-Yub KIM, Yeon Tae JEONG, Byung-Gwon CHO, "Study on Address Discharge Characteristics by Changing Ramp-Down Voltage in AC PDPs" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 9, pp. 1483-1485, September 2011, doi: 10.1587/transele.E94.C.1483.
Abstract: The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1483/_p

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@ARTICLE{e94-c_9_1483,
author={Joon-Yub KIM, Yeon Tae JEONG, Byung-Gwon CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Study on Address Discharge Characteristics by Changing Ramp-Down Voltage in AC PDPs},
year={2011},
volume={E94-C},
number={9},
pages={1483-1485},
abstract={The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.},
keywords={},
doi={10.1587/transele.E94.C.1483},
ISSN={1745-1353},
month={September},}

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TY - JOUR
TI - Study on Address Discharge Characteristics by Changing Ramp-Down Voltage in AC PDPs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1483
EP - 1485
AU - Joon-Yub KIM
AU - Yeon Tae JEONG
AU - Byung-Gwon CHO
PY - 2011
DO - 10.1587/transele.E94.C.1483
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2011
AB - The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.
ER -