In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65 nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Xin ZHANG, Yu PU, Koichi ISHIDA, Yoshikatsu RYU, Yasuyuki OKUMA, Po-Hung CHEN, Takayasu SAKURAI, Makoto TAKAMIYA, "A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 6, pp. 953-959, June 2011, doi: 10.1587/transele.E94.C.953.
Abstract: In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65 nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.953/_p
Copy
@ARTICLE{e94-c_6_953,
author={Xin ZHANG, Yu PU, Koichi ISHIDA, Yoshikatsu RYU, Yasuyuki OKUMA, Po-Hung CHEN, Takayasu SAKURAI, Makoto TAKAMIYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage},
year={2011},
volume={E94-C},
number={6},
pages={953-959},
abstract={In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65 nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.},
keywords={},
doi={10.1587/transele.E94.C.953},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage
T2 - IEICE TRANSACTIONS on Electronics
SP - 953
EP - 959
AU - Xin ZHANG
AU - Yu PU
AU - Koichi ISHIDA
AU - Yoshikatsu RYU
AU - Yasuyuki OKUMA
AU - Po-Hung CHEN
AU - Takayasu SAKURAI
AU - Makoto TAKAMIYA
PY - 2011
DO - 10.1587/transele.E94.C.953
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65 nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.
ER -