0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs

Akira KOTABE; Kiyoo ITOH; Riichiro TAKEMURA

doi:10.1587/transele.E95.C.555

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs

Akira KOTABE, Kiyoo ITOH, Riichiro TAKEMURA

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It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as V_DD is reduced, a boosted word-voltage scheme is first proposed. Second, V_t variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and V_t variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.555-563

Publication Date: 2012/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.555

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)

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Akira KOTABE, Kiyoo ITOH, Riichiro TAKEMURA, "0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 4, pp. 555-563, April 2012, doi: 10.1587/transele.E95.C.555.
Abstract: It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as V_DD is reduced, a boosted word-voltage scheme is first proposed. Second, V_t variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and V_t variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.555/_p

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@ARTICLE{e95-c_4_555,
author={Akira KOTABE, Kiyoo ITOH, Riichiro TAKEMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs},
year={2012},
volume={E95-C},
number={4},
pages={555-563},
abstract={It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as V_DD is reduced, a boosted word-voltage scheme is first proposed. Second, V_t variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and V_t variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.},
keywords={},
doi={10.1587/transele.E95.C.555},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 555
EP - 563
AU - Akira KOTABE
AU - Kiyoo ITOH
AU - Riichiro TAKEMURA
PY - 2012
DO - 10.1587/transele.E95.C.555
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as V_DD is reduced, a boosted word-voltage scheme is first proposed. Second, V_t variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and V_t variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.
ER -