A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits

Xu BAI; Michitaka KAMEYAMA

doi:10.1587/transele.E96.C.1083

A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits

Xu BAI, Michitaka KAMEYAMA

Full Text Views

0

Share
Cite this

Summary :

This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.

Publication: IEICE TRANSACTIONS on Electronics Vol.E96-C No.8 pp.1083-1093

Publication Date: 2013/08/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E96.C.1083

Type of Manuscript: PAPER

Category: Integrated Electronics

Authors

Xu BAI
Tohoku University
Michitaka KAMEYAMA
Tohoku University

Keyword

fine-grain reconfigurable VLSI architecture, multiple-valued switch block, binary-controlled current-steering technique, current-source sharing technique, current-mode logic (CML)

Cite this

Copy

Xu BAI, Michitaka KAMEYAMA, "A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits" in IEICE TRANSACTIONS on Electronics, vol. E96-C, no. 8, pp. 1083-1093, August 2013, doi: 10.1587/transele.E96.C.1083.
Abstract: This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.1083/_p

Copy

@ARTICLE{e96-c_8_1083,
author={Xu BAI, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits},
year={2013},
volume={E96-C},
number={8},
pages={1083-1093},
abstract={This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.},
keywords={},
doi={10.1587/transele.E96.C.1083},
ISSN={1745-1353},
month={August},}

Copy

TY - JOUR
TI - A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1083
EP - 1093
AU - Xu BAI
AU - Michitaka KAMEYAMA
PY - 2013
DO - 10.1587/transele.E96.C.1083
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2013
AB - This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.
ER -