A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design

Li-Rong WANG; Kai-Yu LO; Shyh-Jye JOU

doi:10.1587/transele.E96.C.1351

A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design

Li-Rong WANG, Kai-Yu LO, Shyh-Jye JOU

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This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V_t and 0.84V V_DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V_t technology, as compared to that of the classic double-edge-triggered flip-flop design.

Publication: IEICE TRANSACTIONS on Electronics Vol.E96-C No.10 pp.1351-1355

Publication Date: 2013/10/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E96.C.1351

Type of Manuscript: BRIEF PAPER

Category: Electronic Circuits

Authors

Li-Rong WANG
  National Chiao Tung University
Kai-Yu LO
  National Chiao Tung University
Shyh-Jye JOU
  National Chiao Tung University

Keyword

double-edge-triggered, flip-flop, level-converting, sense amplifier, mixed threshold voltage

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Li-Rong WANG, Kai-Yu LO, Shyh-Jye JOU, "A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design" in IEICE TRANSACTIONS on Electronics, vol. E96-C, no. 10, pp. 1351-1355, October 2013, doi: 10.1587/transele.E96.C.1351.
Abstract: This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V_t and 0.84V V_DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V_t technology, as compared to that of the classic double-edge-triggered flip-flop design.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.1351/_p

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@ARTICLE{e96-c_10_1351,
author={Li-Rong WANG, Kai-Yu LO, Shyh-Jye JOU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design},
year={2013},
volume={E96-C},
number={10},
pages={1351-1355},
abstract={This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V_t and 0.84V V_DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V_t technology, as compared to that of the classic double-edge-triggered flip-flop design.},
keywords={},
doi={10.1587/transele.E96.C.1351},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 1351
EP - 1355
AU - Li-Rong WANG
AU - Kai-Yu LO
AU - Shyh-Jye JOU
PY - 2013
DO - 10.1587/transele.E96.C.1351
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2013
AB - This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V_t and 0.84V V_DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V_t technology, as compared to that of the classic double-edge-triggered flip-flop design.
ER -