A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A<SUP>2</SUP>BC)”

Tadayoshi ENOMOTO; Nobuaki KOBAYASHI

doi:10.1587/transele.E96.C.424

A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A²BC)”

Tadayoshi ENOMOTO, Nobuaki KOBAYASHI

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A motion estimation (ME) multimedia processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast motion estimation (ME) algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled multimedia processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 38.48 µW, which was only 3.261% that of a conventional multimedia processor.

Publication: IEICE TRANSACTIONS on Electronics Vol.E96-C No.4 pp.424-432

Publication Date: 2013/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E96.C.424

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)

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Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, "A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A2BC)”" in IEICE TRANSACTIONS on Electronics, vol. E96-C, no. 4, pp. 424-432, April 2013, doi: 10.1587/transele.E96.C.424.
Abstract: A motion estimation (ME) multimedia processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast motion estimation (ME) algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled multimedia processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 38.48 µW, which was only 3.261% that of a conventional multimedia processor.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.424/_p

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@ARTICLE{e96-c_4_424,
author={Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A2BC)”},
year={2013},
volume={E96-C},
number={4},
pages={424-432},
abstract={A motion estimation (ME) multimedia processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast motion estimation (ME) algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled multimedia processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 38.48 µW, which was only 3.261% that of a conventional multimedia processor.},
keywords={},
doi={10.1587/transele.E96.C.424},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A2BC)”
T2 - IEICE TRANSACTIONS on Electronics
SP - 424
EP - 432
AU - Tadayoshi ENOMOTO
AU - Nobuaki KOBAYASHI
PY - 2013
DO - 10.1587/transele.E96.C.424
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2013
AB - A motion estimation (ME) multimedia processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast motion estimation (ME) algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled multimedia processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 38.48 µW, which was only 3.261% that of a conventional multimedia processor.
ER -