A Design Methodology for Three-Dimensional Hybrid NoC-Bus Architecture

Lei ZHOU; Ning WU; Xin CHEN

doi:10.1587/transele.E96.C.492

A Design Methodology for Three-Dimensional Hybrid NoC-Bus Architecture

Lei ZHOU, Ning WU, Xin CHEN

Full Text Views

0

Share
Cite this

Summary :

Three dimensional integration using Through-Silicon Vias (TSVs) offers short inter-layer interconnects and higher packing density. In order to take advantage of these attributes, a novel hybrid 3D NoC-Bus architecture is proposed in the paper. For vertical link, a Fake Token Bus architecture is elaborated, which utilizes the bandwidth efficiently by updating token synchronously. Based on this bus architecture, a methodology of hybrid 3D NoC-Bus design is introduced. The network hybridizes with the bus in vertical link and distributes long links of the full connected network into different layers, which achieves a network with a diameter of only 3 hops and limited radix. In addition, a congestion-aware routing algorithm applied to the hybrid network is proposed. The algorithm routes packets in horizontal firstly when the bus is busy, which balances the communication and reduces the possibility of congestion. Experimental results show that our network can achieve a 34.4% reduction in latency and a 43% reduction in power consumption under uniform random traffic and a 36.9% reduction in latency and a 48% reduction in power consumption under hotspot traffic over regular 3D mesh implementations on average.

Publication: IEICE TRANSACTIONS on Electronics Vol.E96-C No.4 pp.492-500

Publication Date: 2013/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E96.C.492

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)

Category

Cite this

Copy

Lei ZHOU, Ning WU, Xin CHEN, "A Design Methodology for Three-Dimensional Hybrid NoC-Bus Architecture" in IEICE TRANSACTIONS on Electronics, vol. E96-C, no. 4, pp. 492-500, April 2013, doi: 10.1587/transele.E96.C.492.
Abstract: Three dimensional integration using Through-Silicon Vias (TSVs) offers short inter-layer interconnects and higher packing density. In order to take advantage of these attributes, a novel hybrid 3D NoC-Bus architecture is proposed in the paper. For vertical link, a Fake Token Bus architecture is elaborated, which utilizes the bandwidth efficiently by updating token synchronously. Based on this bus architecture, a methodology of hybrid 3D NoC-Bus design is introduced. The network hybridizes with the bus in vertical link and distributes long links of the full connected network into different layers, which achieves a network with a diameter of only 3 hops and limited radix. In addition, a congestion-aware routing algorithm applied to the hybrid network is proposed. The algorithm routes packets in horizontal firstly when the bus is busy, which balances the communication and reduces the possibility of congestion. Experimental results show that our network can achieve a 34.4% reduction in latency and a 43% reduction in power consumption under uniform random traffic and a 36.9% reduction in latency and a 48% reduction in power consumption under hotspot traffic over regular 3D mesh implementations on average.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.492/_p

Copy

@ARTICLE{e96-c_4_492,
author={Lei ZHOU, Ning WU, Xin CHEN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Design Methodology for Three-Dimensional Hybrid NoC-Bus Architecture},
year={2013},
volume={E96-C},
number={4},
pages={492-500},
abstract={Three dimensional integration using Through-Silicon Vias (TSVs) offers short inter-layer interconnects and higher packing density. In order to take advantage of these attributes, a novel hybrid 3D NoC-Bus architecture is proposed in the paper. For vertical link, a Fake Token Bus architecture is elaborated, which utilizes the bandwidth efficiently by updating token synchronously. Based on this bus architecture, a methodology of hybrid 3D NoC-Bus design is introduced. The network hybridizes with the bus in vertical link and distributes long links of the full connected network into different layers, which achieves a network with a diameter of only 3 hops and limited radix. In addition, a congestion-aware routing algorithm applied to the hybrid network is proposed. The algorithm routes packets in horizontal firstly when the bus is busy, which balances the communication and reduces the possibility of congestion. Experimental results show that our network can achieve a 34.4% reduction in latency and a 43% reduction in power consumption under uniform random traffic and a 36.9% reduction in latency and a 48% reduction in power consumption under hotspot traffic over regular 3D mesh implementations on average.},
keywords={},
doi={10.1587/transele.E96.C.492},
ISSN={1745-1353},
month={April},}

Copy

TY - JOUR
TI - A Design Methodology for Three-Dimensional Hybrid NoC-Bus Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 492
EP - 500
AU - Lei ZHOU
AU - Ning WU
AU - Xin CHEN
PY - 2013
DO - 10.1587/transele.E96.C.492
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2013
AB - Three dimensional integration using Through-Silicon Vias (TSVs) offers short inter-layer interconnects and higher packing density. In order to take advantage of these attributes, a novel hybrid 3D NoC-Bus architecture is proposed in the paper. For vertical link, a Fake Token Bus architecture is elaborated, which utilizes the bandwidth efficiently by updating token synchronously. Based on this bus architecture, a methodology of hybrid 3D NoC-Bus design is introduced. The network hybridizes with the bus in vertical link and distributes long links of the full connected network into different layers, which achieves a network with a diameter of only 3 hops and limited radix. In addition, a congestion-aware routing algorithm applied to the hybrid network is proposed. The algorithm routes packets in horizontal firstly when the bus is busy, which balances the communication and reduces the possibility of congestion. Experimental results show that our network can achieve a 34.4% reduction in latency and a 43% reduction in power consumption under uniform random traffic and a 36.9% reduction in latency and a 48% reduction in power consumption under hotspot traffic over regular 3D mesh implementations on average.
ER -