Robust Cyclic ADC Architecture Based on β-Expansion

Rie SUZUKI; Tsubasa MARUYAMA; Hao SAN; Kazuyuki AIHARA; Masao HOTTA

doi:10.1587/transele.E96.C.553

Robust Cyclic ADC Architecture Based on β-Expansion

Rie SUZUKI, Tsubasa MARUYAMA, Hao SAN, Kazuyuki AIHARA, Masao HOTTA

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In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.

Publication: IEICE TRANSACTIONS on Electronics Vol.E96-C No.4 pp.553-559

Publication Date: 2013/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E96.C.553

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)

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Rie SUZUKI, Tsubasa MARUYAMA, Hao SAN, Kazuyuki AIHARA, Masao HOTTA, "Robust Cyclic ADC Architecture Based on β-Expansion" in IEICE TRANSACTIONS on Electronics, vol. E96-C, no. 4, pp. 553-559, April 2013, doi: 10.1587/transele.E96.C.553.
Abstract: In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.553/_p

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@ARTICLE{e96-c_4_553,
author={Rie SUZUKI, Tsubasa MARUYAMA, Hao SAN, Kazuyuki AIHARA, Masao HOTTA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Robust Cyclic ADC Architecture Based on β-Expansion},
year={2013},
volume={E96-C},
number={4},
pages={553-559},
abstract={In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.},
keywords={},
doi={10.1587/transele.E96.C.553},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Robust Cyclic ADC Architecture Based on β-Expansion
T2 - IEICE TRANSACTIONS on Electronics
SP - 553
EP - 559
AU - Rie SUZUKI
AU - Tsubasa MARUYAMA
AU - Hao SAN
AU - Kazuyuki AIHARA
AU - Masao HOTTA
PY - 2013
DO - 10.1587/transele.E96.C.553
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2013
AB - In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.
ER -