Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration

Li-Chung HSU; Masato MOTOMURA; Yasuhiro TAKE; Tadahiro KURODA

doi:10.1587/transele.E98.C.288

Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration

Li-Chung HSU, Masato MOTOMURA, Yasuhiro TAKE, Tadahiro KURODA

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This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.

Publication: IEICE TRANSACTIONS on Electronics Vol.E98-C No.4 pp.288-297

Publication Date: 2015/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E98.C.288

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)

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Authors

Li-Chung HSU
  Keio University
Masato MOTOMURA
  Hokkaido University
Yasuhiro TAKE
  Keio University
Tadahiro KURODA
  Keio University

Keyword

TCI, ThruChip, 3-D FPGA, TSV, FPGA, TPR, VPR

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Li-Chung HSU, Masato MOTOMURA, Yasuhiro TAKE, Tadahiro KURODA, "Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration" in IEICE TRANSACTIONS on Electronics, vol. E98-C, no. 4, pp. 288-297, April 2015, doi: 10.1587/transele.E98.C.288.
Abstract: This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.288/_p

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@ARTICLE{e98-c_4_288,
author={Li-Chung HSU, Masato MOTOMURA, Yasuhiro TAKE, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration},
year={2015},
volume={E98-C},
number={4},
pages={288-297},
abstract={This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.},
keywords={},
doi={10.1587/transele.E98.C.288},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
T2 - IEICE TRANSACTIONS on Electronics
SP - 288
EP - 297
AU - Li-Chung HSU
AU - Masato MOTOMURA
AU - Yasuhiro TAKE
AU - Tadahiro KURODA
PY - 2015
DO - 10.1587/transele.E98.C.288
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2015
AB - This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.
ER -