Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing

Zhou JIANG; Guiming LUO; Kele SHEN

doi:10.1587/transele.E99.C.1071

Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing

Zhou JIANG, Guiming LUO, Kele SHEN

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The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.

Publication: IEICE TRANSACTIONS on Electronics Vol.E99-C No.9 pp.1071-1079

Publication Date: 2016/09/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E99.C.1071

Type of Manuscript: PAPER

Category: Electronic Circuits

Authors

Zhou JIANG
  Tsinghua University
Guiming LUO
  Tsinghua University
Kele SHEN
  Tsinghua University

Keyword

scan test, scan segmentation, lower power testing, complex networks clustering, design for testability, at-speed testing

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Zhou JIANG, Guiming LUO, Kele SHEN, "Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing" in IEICE TRANSACTIONS on Electronics, vol. E99-C, no. 9, pp. 1071-1079, September 2016, doi: 10.1587/transele.E99.C.1071.
Abstract: The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.1071/_p

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@ARTICLE{e99-c_9_1071,
author={Zhou JIANG, Guiming LUO, Kele SHEN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing},
year={2016},
volume={E99-C},
number={9},
pages={1071-1079},
abstract={The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.},
keywords={},
doi={10.1587/transele.E99.C.1071},
ISSN={1745-1353},
month={September},}

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TY - JOUR
TI - Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing
T2 - IEICE TRANSACTIONS on Electronics
SP - 1071
EP - 1079
AU - Zhou JIANG
AU - Guiming LUO
AU - Kele SHEN
PY - 2016
DO - 10.1587/transele.E99.C.1071
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2016
AB - The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.
ER -