A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link

Kaoru KOHIRA; Hiroki ISHIKURO

doi:10.1587/transele.E99.C.458

A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link

Kaoru KOHIRA, Hiroki ISHIKURO

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This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10^-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm².

Publication: IEICE TRANSACTIONS on Electronics Vol.E99-C No.4 pp.458-465

Publication Date: 2016/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E99.C.458

Type of Manuscript: PAPER

Category: Electronic Circuits

Authors

Kaoru KOHIRA
Keio University
Hiroki ISHIKURO
Keio University

Keyword

CDR, injection locking, edge detectors, high speed

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Kaoru KOHIRA, Hiroki ISHIKURO, "A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link" in IEICE TRANSACTIONS on Electronics, vol. E99-C, no. 4, pp. 458-465, April 2016, doi: 10.1587/transele.E99.C.458.
Abstract: This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10^-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm².
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.458/_p

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@ARTICLE{e99-c_4_458,
author={Kaoru KOHIRA, Hiroki ISHIKURO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link},
year={2016},
volume={E99-C},
number={4},
pages={458-465},
abstract={This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10^-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm².},
keywords={},
doi={10.1587/transele.E99.C.458},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link
T2 - IEICE TRANSACTIONS on Electronics
SP - 458
EP - 465
AU - Kaoru KOHIRA
AU - Hiroki ISHIKURO
PY - 2016
DO - 10.1587/transele.E99.C.458
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2016
AB - This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10^-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm².
ER -