Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology

Tian WANG; Xiaoxin CUI; Kai LIAO; Nan LIAO; Xiaole CUI; Dunshan YU

doi:10.1587/transele.E99.C.974

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology

Tian WANG, Xiaoxin CUI, Kai LIAO, Nan LIAO, Xiaole CUI, Dunshan YU

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With the decrease in transistor feature size, power consumption, especially leakage power, has become a most important design concern. Because of their superior electrical properties and design flexibility, fin-type field-effect transistors (FinFETs) seem to be the most promising option in low-power applications. In order to support the VLSI digital system design flow based on logic synthesis, this paper proposes a design method for low-power high-performance standard cells based on IG-mode FinFETs. Such a method is derived on the basis of appropriately and artfully designing and optimizing the stacked structures in each standard cell, and applying the mixed forward and reverse back-gate bias technique in a well-chosen manner. The proposed method is also applicable when the supply voltage reduces to 0.5V to further reduce the leakage power consumption. By applying this design method, optimized IG-mode FinFET standard cells are generated, and they form a low-power high-performance standard cell library. Simulation results of the library cells indicate that the performance of the standard cells designed with the proposed method can be maintained while reducing leakage consumption by a factor of 58.9 at most. The 16-bit ripple carry adder implemented with this library can acquire up to 17.5% leakage power reduction.

Publication: IEICE TRANSACTIONS on Electronics Vol.E99-C No.8 pp.974-983

Publication Date: 2016/08/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E99.C.974

Type of Manuscript: PAPER

Category: Electronic Circuits

Authors

Tian WANG
  Peking University
Xiaoxin CUI
  Peking University
Kai LIAO
  Peking University
Nan LIAO
  Peking University
Xiaole CUI
  Peking University Shenzhen Graduate School
Dunshan YU
  Peking University

Keyword

VLSI, FinFET, standard cell, stacking, back biasing

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Tian WANG, Xiaoxin CUI, Kai LIAO, Nan LIAO, Xiaole CUI, Dunshan YU, "Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology" in IEICE TRANSACTIONS on Electronics, vol. E99-C, no. 8, pp. 974-983, August 2016, doi: 10.1587/transele.E99.C.974.
Abstract: With the decrease in transistor feature size, power consumption, especially leakage power, has become a most important design concern. Because of their superior electrical properties and design flexibility, fin-type field-effect transistors (FinFETs) seem to be the most promising option in low-power applications. In order to support the VLSI digital system design flow based on logic synthesis, this paper proposes a design method for low-power high-performance standard cells based on IG-mode FinFETs. Such a method is derived on the basis of appropriately and artfully designing and optimizing the stacked structures in each standard cell, and applying the mixed forward and reverse back-gate bias technique in a well-chosen manner. The proposed method is also applicable when the supply voltage reduces to 0.5V to further reduce the leakage power consumption. By applying this design method, optimized IG-mode FinFET standard cells are generated, and they form a low-power high-performance standard cell library. Simulation results of the library cells indicate that the performance of the standard cells designed with the proposed method can be maintained while reducing leakage consumption by a factor of 58.9 at most. The 16-bit ripple carry adder implemented with this library can acquire up to 17.5% leakage power reduction.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.974/_p

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@ARTICLE{e99-c_8_974,
author={Tian WANG, Xiaoxin CUI, Kai LIAO, Nan LIAO, Xiaole CUI, Dunshan YU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology},
year={2016},
volume={E99-C},
number={8},
pages={974-983},
abstract={With the decrease in transistor feature size, power consumption, especially leakage power, has become a most important design concern. Because of their superior electrical properties and design flexibility, fin-type field-effect transistors (FinFETs) seem to be the most promising option in low-power applications. In order to support the VLSI digital system design flow based on logic synthesis, this paper proposes a design method for low-power high-performance standard cells based on IG-mode FinFETs. Such a method is derived on the basis of appropriately and artfully designing and optimizing the stacked structures in each standard cell, and applying the mixed forward and reverse back-gate bias technique in a well-chosen manner. The proposed method is also applicable when the supply voltage reduces to 0.5V to further reduce the leakage power consumption. By applying this design method, optimized IG-mode FinFET standard cells are generated, and they form a low-power high-performance standard cell library. Simulation results of the library cells indicate that the performance of the standard cells designed with the proposed method can be maintained while reducing leakage consumption by a factor of 58.9 at most. The 16-bit ripple carry adder implemented with this library can acquire up to 17.5% leakage power reduction.},
keywords={},
doi={10.1587/transele.E99.C.974},
ISSN={1745-1353},
month={August},}

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TY - JOUR
TI - Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 974
EP - 983
AU - Tian WANG
AU - Xiaoxin CUI
AU - Kai LIAO
AU - Nan LIAO
AU - Xiaole CUI
AU - Dunshan YU
PY - 2016
DO - 10.1587/transele.E99.C.974
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2016
AB - With the decrease in transistor feature size, power consumption, especially leakage power, has become a most important design concern. Because of their superior electrical properties and design flexibility, fin-type field-effect transistors (FinFETs) seem to be the most promising option in low-power applications. In order to support the VLSI digital system design flow based on logic synthesis, this paper proposes a design method for low-power high-performance standard cells based on IG-mode FinFETs. Such a method is derived on the basis of appropriately and artfully designing and optimizing the stacked structures in each standard cell, and applying the mixed forward and reverse back-gate bias technique in a well-chosen manner. The proposed method is also applicable when the supply voltage reduces to 0.5V to further reduce the leakage power consumption. By applying this design method, optimized IG-mode FinFET standard cells are generated, and they form a low-power high-performance standard cell library. Simulation results of the library cells indicate that the performance of the standard cells designed with the proposed method can be maintained while reducing leakage consumption by a factor of 58.9 at most. The 16-bit ripple carry adder implemented with this library can acquire up to 17.5% leakage power reduction.
ER -