A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

Yuichiro MURACHI; Koji HAMANO; Tetsuro MATSUNO; Junichi MIYAKOSHI; Masayuki MIYAMA; Masahiko YOSHIMOTO

doi:10.1093/ietfec/e88-a.12.3492

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Junichi MIYAKOSHI, Masayuki MIYAMA, Masahiko YOSHIMOTO

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This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 19201080@30 fps resolution video. The search range is 12864 pixels. The ME core integrates 2.25 M transistors in 3.1 mm3.1 mm using 0.18-micron technology.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3492-3499

Publication Date: 2005/12/01

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DOI: 10.1093/ietfec/e88-a.12.3492

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: VLSI Architecture

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Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Junichi MIYAKOSHI, Masayuki MIYAMA, Masahiko YOSHIMOTO, "A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 12, pp. 3492-3499, December 2005, doi: 10.1093/ietfec/e88-a.12.3492.
Abstract: This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 19201080@30 fps resolution video. The search range is 12864 pixels. The ME core integrates 2.25 M transistors in 3.1 mm3.1 mm using 0.18-micron technology.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3492/_p

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@ARTICLE{e88-a_12_3492,
author={Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Junichi MIYAKOSHI, Masayuki MIYAMA, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application},
year={2005},
volume={E88-A},
number={12},
pages={3492-3499},
abstract={This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 19201080@30 fps resolution video. The search range is 12864 pixels. The ME core integrates 2.25 M transistors in 3.1 mm3.1 mm using 0.18-micron technology.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3492},
ISSN={},
month={December},}

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TY - JOUR
TI - A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3492
EP - 3499
AU - Yuichiro MURACHI
AU - Koji HAMANO
AU - Tetsuro MATSUNO
AU - Junichi MIYAKOSHI
AU - Masayuki MIYAMA
AU - Masahiko YOSHIMOTO
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3492
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 19201080@30 fps resolution video. The search range is 12864 pixels. The ME core integrates 2.25 M transistors in 3.1 mm3.1 mm using 0.18-micron technology.
ER -