Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators

Jaesang LIM; Jaejoon KIM; Beomsup KIM

doi:10.1093/ietfec/e88-a.4.1084

Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators

Jaesang LIM, Jaejoon KIM, Beomsup KIM

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A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.4 pp.1084-1089

Publication Date: 2005/04/01

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DOI: 10.1093/ietfec/e88-a.4.1084

Type of Manuscript: PAPER

Category: General Fundamentals and Boundaries

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Jaesang LIM, Jaejoon KIM, Beomsup KIM, "Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 4, pp. 1084-1089, April 2005, doi: 10.1093/ietfec/e88-a.4.1084.
Abstract: A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.4.1084/_p

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@ARTICLE{e88-a_4_1084,
author={Jaesang LIM, Jaejoon KIM, Beomsup KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators},
year={2005},
volume={E88-A},
number={4},
pages={1084-1089},
abstract={A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.},
keywords={},
doi={10.1093/ietfec/e88-a.4.1084},
ISSN={},
month={April},}

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TY - JOUR
TI - Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1084
EP - 1089
AU - Jaesang LIM
AU - Jaejoon KIM
AU - Beomsup KIM
PY - 2005
DO - 10.1093/ietfec/e88-a.4.1084
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2005
AB - A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.
ER -