Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

Akira TSUCHIYA; Masanori HASHIMOTO; Hidetoshi ONODERA

doi:10.1093/ietfec/e88-a.4.885

Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

Akira TSUCHIYA, Masanori HASHIMOTO, Hidetoshi ONODERA

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This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.4 pp.885-891

Publication Date: 2005/04/01

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DOI: 10.1093/ietfec/e88-a.4.885

Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)

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Akira TSUCHIYA, Masanori HASHIMOTO, Hidetoshi ONODERA, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 4, pp. 885-891, April 2005, doi: 10.1093/ietfec/e88-a.4.885.
Abstract: This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.4.885/_p

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@ARTICLE{e88-a_4_885,
author={Akira TSUCHIYA, Masanori HASHIMOTO, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling},
year={2005},
volume={E88-A},
number={4},
pages={885-891},
abstract={This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.},
keywords={},
doi={10.1093/ietfec/e88-a.4.885},
ISSN={},
month={April},}

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TY - JOUR
TI - Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 885
EP - 891
AU - Akira TSUCHIYA
AU - Masanori HASHIMOTO
AU - Hidetoshi ONODERA
PY - 2005
DO - 10.1093/ietfec/e88-a.4.885
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2005
AB - This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.
ER -