Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion

Yukihide KOHIRA; Atsushi TAKAHASHI

doi:10.1093/ietfec/e88-a.4.892

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion

Yukihide KOHIRA, Atsushi TAKAHASHI

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Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced if delays between some registers are increased by delay insertion. In this paper, we propose a delay insertion algorithm to reduce the minimum clock period. First, the proposed algorithm determines a clock schedule ignoring some constraints. Second, the algorithm inserts delays to recover ignored constraints according to the delay-slack and delay-demand of the obtained clock schedule. We show that the proposed algorithm achieves the minimum clock period by delay insertion if the delay of each element in the circuit is unique. Experiments show that the amount of inserting delay and computational time are smaller than the conventional algorithm.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.4 pp.892-898

Publication Date: 2005/04/01

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DOI: 10.1093/ietfec/e88-a.4.892

Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)

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Yukihide KOHIRA, Atsushi TAKAHASHI, "Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 4, pp. 892-898, April 2005, doi: 10.1093/ietfec/e88-a.4.892.
Abstract: Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced if delays between some registers are increased by delay insertion. In this paper, we propose a delay insertion algorithm to reduce the minimum clock period. First, the proposed algorithm determines a clock schedule ignoring some constraints. Second, the algorithm inserts delays to recover ignored constraints according to the delay-slack and delay-demand of the obtained clock schedule. We show that the proposed algorithm achieves the minimum clock period by delay insertion if the delay of each element in the circuit is unique. Experiments show that the amount of inserting delay and computational time are smaller than the conventional algorithm.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.4.892/_p

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@ARTICLE{e88-a_4_892,
author={Yukihide KOHIRA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion},
year={2005},
volume={E88-A},
number={4},
pages={892-898},
abstract={Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced if delays between some registers are increased by delay insertion. In this paper, we propose a delay insertion algorithm to reduce the minimum clock period. First, the proposed algorithm determines a clock schedule ignoring some constraints. Second, the algorithm inserts delays to recover ignored constraints according to the delay-slack and delay-demand of the obtained clock schedule. We show that the proposed algorithm achieves the minimum clock period by delay insertion if the delay of each element in the circuit is unique. Experiments show that the amount of inserting delay and computational time are smaller than the conventional algorithm.},
keywords={},
doi={10.1093/ietfec/e88-a.4.892},
ISSN={},
month={April},}

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TY - JOUR
TI - Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 892
EP - 898
AU - Yukihide KOHIRA
AU - Atsushi TAKAHASHI
PY - 2005
DO - 10.1093/ietfec/e88-a.4.892
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2005
AB - Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced if delays between some registers are increased by delay insertion. In this paper, we propose a delay insertion algorithm to reduce the minimum clock period. First, the proposed algorithm determines a clock schedule ignoring some constraints. Second, the algorithm inserts delays to recover ignored constraints according to the delay-slack and delay-demand of the obtained clock schedule. We show that the proposed algorithm achieves the minimum clock period by delay insertion if the delay of each element in the circuit is unique. Experiments show that the amount of inserting delay and computational time are smaller than the conventional algorithm.
ER -